1. Field of the Invention
The present invention relates to a wiring pattern of a multilayer printed wiring board mounting a semiconductor device.
2. Related Background Art
A printed circuit board in which a semiconductor device is mounted on a printed wiring board has been used so far for various products. Because wirings of a printed wiring board are increased in density, the BGA method and the CSP method for connecting a semiconductor device with a printed wiring board by a plurality of solder balls arranged like an array have been frequently used. Moreover, a multilayer printed wiring board is generally used.
It is requested for a solder ball for connecting a semiconductor device with a printed wiring board to keep a desired joint strength. To keep the joint strength, it is necessary to minimize a relative deformation between the printed wiring board and the semiconductor device.
However, the printed wiring board is exposed to a high temperature of 200° C. or higher in a heating-cooling process such as a solder reflow process. Moreover, the coefficient of thermal expansion of epoxy resin or glass epoxy resin for forming the printed wiring board is larger than the coefficient of thermal expansion of an IC chip comprising silicon forming a semiconductor device by approximately 10 times. Therefore, in the solder reflow process, the elongation of the printed wiring board becomes larger than the elongation of a semiconductor device including an IC chip having a small coefficient of thermal expansion. Because of the difference between the coefficients of thermal expansion, the printed wiring board greatly warps and thereby, a large stress is applied to a solder ball. Therefore, a crack occurs on the solder ball or the joint between the semiconductor device and the printed wiring board is disconnected.
As a means for reducing the warp, it is known to minimize the coefficient of thermal expansion of the printed wiring board. Japanese Patent Application Laid-Open No. 2002-100880 (Patent Document 1) discloses a method for preventing the warp of a multilayer printed wiring board due to thermal expansion and reducing a stress applied to a solder joint portion. That is, a plurality of lands are formed on the surface of a multilayer printed wiring board, a semiconductor device is mounted by solder, and a solid ground layer made of a metal, such as copper, of an inner layer of the multilayer printed wiring board is formed by punching a circular or hexagonal continuous pattern. Thereby, the thermal expansion coefficient of the printed wiring board is decreased and the warp of the printed wiring board is prevented.
Moreover, Japanese Patent Application Laid-Open No. H05-343820 (Patent Document 2) discloses that a solid ground layer of an inner layer of a printed wiring board as in Patent Document 1 is formed into a shape a continuous pattern of a circle or polygon such as a hexagon obtained by punching. Moreover, its purpose is to adjust the characteristic impedance of a signal wiring set to a wiring layer adjacent to the ground layer. That is, the characteristic impedance value of the signal wiring set to the adjacent wiring layer is adjusted in accordance with the size or shape of a circular or hexagonal continuous pattern. Thereby, it is possible to realize impedance matching of a wiring and obtain the propagation characteristic of a high-speed stable electric signal.
In recent years, because a product is downsized and has an advanced function, the wiring of a printed wiring board is further increased in density and the size of a solder ball for connecting a semiconductor device with the printed wiring board is further decreased. Therefore, how to maintain a joint strength by small solder ball is a large problem. Moreover, the thickness of a printed wiring board is decreased and the number of wiring pattern layers made of a metal such as a copper foil is increased. Therefore, the coefficient of thermal expansion and the stiffness of a printed wiring board are raised and the difference between coefficients of thermal expansion of a semiconductor device and a printed wiring board is increased.
In the case of a method for forming a continuous pattern of a circle or polygon such as a hexagon on a solid ground layer of an inner layer disclosed in Patent Documents 1 and 2, to stabilize the wiring impedance of the whole wiring layer, it is effective to minimize the size of the continuous pattern of circle or polygon such as a hexagon. However, when the size of the continuous pattern of circle or polygon such as a hexagon is decreased, the coefficient of thermal expansion of a printed wiring board increases and the above problem of warp is actualized.